- Division is continued subtraction till remainder is less than divisor
- D Flip flops are used as PIPO registers
- For full adder, carry out = 1, if remainder > divisor, ie, continue continued subtraction
Cout = 0, if remainder < divisor, ie, end the process
A blog to find answers to questions based on Electronics & Communication Engineering, CUSAT.
Blog Archive
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2013
(13)
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November
(13)
- Binary Division - Main points to write
- Transfer Characteristics Of TTL
- Race Around Condition
- Static & Dynamic Resistances Of Diodes
- To determine reverse saturation current of diode
- 0-1-1-1-3-4-5-7 Synchronous Sequence Generator - M...
- Octal Counter Using 7490 ( 74LS90 )
- Octal Counter - 74LS93
- 9-27 COUNTER
- 4:2 High Priority Encoder
- Asynchronous 0-2-4-5 counter
- 8 Bit adder
- 0-1-1-1-3-4-5-7 Synchronous Pattern Generator
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November
(13)
Tuesday, November 26, 2013
Binary Division - Main points to write
Tuesday, November 5, 2013
Static & Dynamic Resistances Of Diodes
Static : DC Resistance. Measured by considering V & I of a single point
Dynamic : AC Resistance, measured by considering a small change in the values of v & i. Take 2 points and the difference in the values of V, I while calculating.
Dynamic : AC Resistance, measured by considering a small change in the values of v & i. Take 2 points and the difference in the values of V, I while calculating.
To determine reverse saturation current of diode
Obtain the forward characteristics of the diode. Note any V & I after the knee voltage.
Substitute in equation;
I = Io(e^(V/nVT) - 1 )
n = 1 for Ge, 2 for Si
Vt = 26mV
Find reverse saturation current !
Or reverse bias the diode & determine the current flowing through using uA
Substitute in equation;
I = Io(e^(V/nVT) - 1 )
n = 1 for Ge, 2 for Si
Vt = 26mV
Find reverse saturation current !
Or reverse bias the diode & determine the current flowing through using uA
Monday, November 4, 2013
Sunday, November 3, 2013
9-27 COUNTER
Tips : If Rs of second counter R1,R2 are set to high, output will be 9
If Rs of first counter are set to high, output will be 0;
Circuit needs initial setting to 9; using the third logic gate as high ( third from top )
Proteus File
Circuit :
If Rs of first counter are set to high, output will be 0;
Circuit needs initial setting to 9; using the third logic gate as high ( third from top )
Proteus File
Circuit :
Asynchronous 0-2-4-5 counter
Hint : Design Mod 4 async counter, and force the outputs to required states,
ie, 00 -> 000
01 -> 010
10 -> 100
11 -> 101
Proteus File ( Incase of error with clock, just replace the clock with the same part and it should work fine )
ie, 00 -> 000
01 -> 010
10 -> 100
11 -> 101
Proteus File ( Incase of error with clock, just replace the clock with the same part and it should work fine )
0-1-1-1-3-4-5-7 Synchronous Pattern Generator
Hints :
No of flip-flops required JK 7476 : 5
No of flip-flops whose outputs are taken as output of circuit : 3 ( The least significant 3 digits )
T5,T4,T3,T2,T1 : Inputs of Flipflops
D5,D4,D3,D2,D1 : Outputs ( D3-D1 : Output of the circuit )
t5 = d4+d5
t4 = d5d3d2d1
t3 = d2
t2 = d5+d2+d3d2d1
t1 = d2d1+d2d1
Note : Expressions may be further simplified using K-map
Proteus 8 Simulation File : Download
Circuit Diagram :
No of flip-flops required JK 7476 : 5
No of flip-flops whose outputs are taken as output of circuit : 3 ( The least significant 3 digits )
T5,T4,T3,T2,T1 : Inputs of Flipflops
D5,D4,D3,D2,D1 : Outputs ( D3-D1 : Output of the circuit )
t5 = d4+d5
t4 = d5d3d2d1
t3 = d2
t2 = d5+d2+d3d2d1
t1 = d2d1+d2d1
Note : Expressions may be further simplified using K-map
Proteus 8 Simulation File : Download
Circuit Diagram :
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